1. Field of the Invention
This invention relates to a method for fabricating a gallium nitride-based (GaN-based) thin film transistor, more particularly to a method for fabricating an enhancement mode (E-mode) GaN-based thin film transistor.
2. Description of the Related Art
Referring to FIG. 1, a conventional GaN-based thin film transist or includes a substrate 11, a semiconductor layer 12, a dielectric layer 13 disposed on a top surface of the semiconductor layer 12, source and drain electrodes 15, 16 respectively formed on two opposite sides of the dielectric layer 13, and a gate electrode 14 disposed on a top surface of the dielectric layer 13 and between the source and drain electrodes 15, 16. The semiconductor layer 12 includes, from bottom to top, a first GaN epitaxial film 121 formed on the substrate 11, an aluminum gallium nitride (AlGaN) epitaxial film 122, and a second GaN epitaxial film 123 connected to the dielectric layer 13.
In the conventional GaN-based thin film transistor, since two dimensional electron gas (2DEG) is induced by a mass of polarization charges in the first GaN epitaxial film 121 and the AlGaN epitaxial film 122, the transistor is required to be operated in a depletion-mode. Such transistor is also referred to as a “normally on” transistor. The “normally on” transistor has a negative threshold voltage, and thus, consumes power even at zero gate bias. This results in additional power loss. Besides, when the transistor is used in a high power circuit system, a transient pulse voltage is likely to occur since the high power circuit system is required to be operated at an extremely high bias voltage. A malfunction of the high power circuit system caused by the “abnormally on” state of the high power element (the transistor) tends to occur due to insufficient high threshold voltage of the transistor. Hence, the stability of the high power circuit system may be adversely affected.
In order to provide an improved GaN thin film transistor that has a relatively high threshold voltage, an improved high voltage endurance, and a relatively high power output, and that is operated at an enhancement mode (E-mode), U.S. Pat. No. 7,655,962 discloses an enhancement mode transistor including a bottom AlInGaN barrier layer disposed under an AlInGaN channel layer so that polarization charges of the bottom barrier layer deplete charges in the channel layer. The transistor of U.S. Pat. No. 7,655,962 also includes a gate electrode formed as a deep recessed gate so that the transistor is in the off state at zero gate bias.
Furthermore, U.S. Patent Application Publication No. 2007/0295993 discloses a high electron mobility transistor made by introducing fluorine ions into an AlInGaN channel layer using a CF4 plasma treatment to effectively deplete charges in the AlInGaN channel layer. Accordingly, the transistor is in the off state at zero gate bias, and can serve as an E-mode transistor.
However, formation of the deep recessed gate described in U.S. Pat. No. 7,655,962 requires a surface etching process. This may result in an increased surface state density of the transistor that is likely to adversely affect current characteristics and reliability of the transistor. Besides, although the threshold voltage of the transistor described in U.S. Patent Application Publication No. 2007/0295993 can be increased by introducing the fluorine ions using the CF4 plasma treatment, it can be increased only by 0.9 volt due to a limited diffusion capability of the fluorine ions, and is thus unsatisfactory.